COMMON ATTACK PATTERN ENUMERATION AND CLASSIFICATIONLive MITRE record

CAPEC-674

Design for FPGA Maliciously Altered

An adversary alters the functionality of a field-programmable gate array (FPGA) by causing an FPGA configuration memory chip reload in order to introduce a malicious function that could result in the FPGA performing or enabling malicious functions on a host system. Prior to the memory chip reload, the adversary alters the program for the FPGA by adding a function to impact system operation.

Abstraction

Detailed

Typical severity

High

Likelihood of attack

Low

Understand the attack

What is this attack pattern?

An adversary alters the functionality of a field-programmable gate array (FPGA) by causing an FPGA configuration memory chip reload in order to introduce a malicious function that could result in the FPGA performing or enabling malicious functions on a host system. Prior to the memory chip reload, the adversary alters the program for the FPGA by adding a function to impact system operation.

Requirements

What does the attack require?

Prerequisites

  • An adversary would need to have access to FPGA programming/configuration-related systems in a chip maker’s development environment where FPGAs can be initially configured prior to delivery to a customer or have access to such systems in a customer facility where end-user FPGA configuration/reconfiguration can be performed.

Skills required

  • High: An adversary would need to be skilled in FPGA programming in order to create/manipulate configurations in such a way that when loaded into an FPGA, the end user would be able to observe through testing all user-defined required functions but would be unaware of any additional functions the adversary may have introduced.

Resources required

Not stated in the MITRE record.

Impact

What does a successful attack lead to?

Alter Execution Logic

Affected scopes: Integrity

Defence

How is it prevented and mitigated?

1
Utilize DMEA’s (Defense Microelectronics Activity) Trusted Foundry Program members for acquisition of microelectronic components.
2
Ensure that each supplier performing hardware development implements comprehensive, security-focused configuration management including for FPGA programming and program uploads to FPGA chips.
3
Require that provenance of COTS microelectronic components be known whenever procured.
4
Conduct detailed vendor assessment before acquiring COTS hardware.

Real world

MITRE example instances

Example instance 1Detail
An adversary with access and the ability to alter the configuration/programming of FPGAs in organizational systems, introduces a trojan backdoor that can be used to alter the behavior of the original system resulting in, for example, compromise of confidentiality of data being processed.
CAPEC-674: Design for FPGA Maliciously Altered — DayBreach Saldırı Sözlüğü · DayBreach