COMMON WEAKNESS ENUMERATIONDraft

CWE-1239

Improper Zeroization of Hardware Register

The hardware product does not properly clear sensitive information from built-in registers when the user of the hardware block changes.

Abstraction

Variant

Structure

Simple

Likelihood of Exploit

Medium

Understand the problem

What is the problem?

The hardware product does not properly clear sensitive information from built-in registers when the user of the hardware block changes.

Extended description

Hardware logic operates on data stored in registers local to the hardware block. Most hardware IPs, including cryptographic accelerators, rely on registers to buffer I/O, store intermediate values, and interface with software. The result of this is that sensitive information, such as passwords or encryption keys, can exist in locations not transparent to the user of the hardware logic. When a different entity obtains access to the IP due to a change in operating mode or conditions, the new entity can extract information belonging to the previous user if no mechanisms are in place to clear register contents. It is important to clear information stored in the hardware if a physical attack on the product is detected, or if the user of the hardware block changes. The process of clearing register contents in a hardware IP is referred to as zeroization in standards for cryptographic hardware modules such as FIPS-140-2 [REF-267].

Root cause

How and when does the problem arise?

Lifecycle phase

Architecture and Design

Lack of hardware mechanisms to zeroize or clear registers in the design or specification.

Lifecycle phase

Implementation

Mechanisms to zeroize and clear registers are in the design but implemented incorrectly.

Lifecycle phase

Operation

Hardware-provided zeroization mechanisms are not used appropriately by the IP user (ex. firmware), or data remanence issues are not taken into account.

Risk

What does successful exploitation lead to?

Varies by Context

Affected security scopes: Confidentiality

The consequences will depend on the information disclosed due to the vulnerability.

Defence

How is it prevented and fixed?

Architecture and Design

Architecture and design approach

Detail
Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

Unfortunately, data disclosure can occur even after information has been overwritten/zeroized from the digital perspective. Physical characteristics of the memory can reveal the history of previously written data. For example, if the same value is written repeatedly to a memory location, the corresponding memory cells can become physically altered to a degree that even if the original data is erased it can still be recovered through physical characterization of the memory cells [REF-1055].