COMMON WEAKNESS ENUMERATIONDraft

CWE-1298

Hardware Logic Contains Race Conditions

A race condition in the hardware logic results in undermining security guarantees of the system.

Abstraction

Base

Structure

Simple

Likelihood of Exploit

Medium

Understand the problem

What is the problem?

A race condition in the hardware logic results in undermining security guarantees of the system.

Extended description

A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that have traversed different paths while originating from the same source. Such inputs to the gate can change at slightly different times in response to a change in the source signal. This results in a timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted state before settling back to the desired state. If such timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections.

Root cause

How and when does the problem arise?

Lifecycle phase

Architecture and Design

Lifecycle phase

Implementation

Risk

What does successful exploitation lead to?

Bypass Protection MechanismGain Privileges or Assume IdentityAlter Execution Logic

Affected security scopes: Access Control

Defence

How is it prevented and fixed?

Architecture and Design

Architecture and design approach

Detail
Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.

Implementation

Implementation-phase defence

Detail
Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.