COMMON WEAKNESS ENUMERATIONIncomplete

CWE-1342

Information Exposure through Microarchitectural State after Transient Execution

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

Abstraction

Base

Structure

Simple

Likelihood of Exploit

Medium

Understand the problem

What is the problem?

The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.

Extended description

In many processor architectures an exception, mis-speculation, or microcode assist results in a flush operation to clear results that are no longer required. This action prevents these results from influencing architectural state that is intended to be visible from software. However, traces of this transient execution may remain in microarchitectural buffers, resulting in a change in microarchitectural state that can expose sensitive information to an attacker using side-channel analysis. For example, Load Value Injection (LVI) [REF-1202] can exploit direct injection of erroneous values into intermediate load and store buffers. Several conditions may need to be fulfilled for a successful attack: 1. incorrect transient execution that results in remanence of sensitive information; 1. attacker has the ability to provoke microarchitectural exceptions; 1. operations and structures in victim code that can be exploited must be identified.

Root cause

How and when does the problem arise?

Lifecycle phase

Architecture and Design

Lifecycle phase

Requirements

Risk

What does successful exploitation lead to?

Modify MemoryRead MemoryExecute Unauthorized Code or Commands

Affected security scopes: Confidentiality, Integrity

Defence

How is it prevented and fixed?

Architecture and Design · Requirements

Defence to apply across several lifecycle phases

Detail
Hardware ensures that no illegal data flows from faulting micro-ops exists at the microarchitectural level.

Effectiveness: High

Being implemented in silicon it is expected to fully address the known weaknesses with limited performance impact.

Build and Compilation

Build and Compilation aşaması savunması

Detail
Include instructions that explicitly remove traces of unneeded computations from software interactions with microarchitectural elements e.g. lfence, sfence, mfence, clflush.

Effectiveness: High

This effectively forces the processor to complete each memory access before moving on to the next operation. This may have a large performance impact.