COMMON ATTACK PATTERN ENUMERATION AND CLASSIFICATIONLive MITRE record

CAPEC-702

Exploiting Incorrect Chaining or Granularity of Hardware Debug Components

An adversary exploits incorrect chaining or granularity of hardware debug components in order to gain unauthorized access to debug functionality on a chip. This happens when authorization is not checked on a per function basis and is assumed for a chain or group of debug functionality.

Abstraction

Detailed

Typical severity

Medium

Likelihood of attack

Low

Understand the attack

What is this attack pattern?

An adversary exploits incorrect chaining or granularity of hardware debug components in order to gain unauthorized access to debug functionality on a chip. This happens when authorization is not checked on a per function basis and is assumed for a chain or group of debug functionality.

Extended description

Chip designers often include design elements in a chip for debugging and troubleshooting such as: Various Test Access Ports (TAPs) which allow boundary scan commands to be executed. Scan cells that allow the chip to be used as a "stimulus and response" mechanism for scanning the internal components of a chip. Custom methods to observe the internal components of their chips by placing various tracing hubs within their chip and creating hierarchical or interconnected structures among those hubs. Because devices commonly have multiple chips and debug components, designers will connect debug components and expose them through a single external interface, which is referred to as “chaining”. Logic errors during design or synthesis could misconfigure the chaining of the debug components, which could allow unintended access. TAPs are also commonly referred to as JTAG interfaces.

Execution flow

How does the attack proceed, step by step?

1

Explore

Find and scan debug interface

The adversary must first find and scan a debug interface to determine what they are authorized to use and what devices are chained to that interface.

Techniques used

  • Use a JTAGulator on a JTAG interface to determine the correct pin configuration, baud rate, and number of devices in the chain
2

Experiment

Connect to debug interface

The adversary next connects a device to the JTAG interface using the properties found in the explore phase so that they can send commands. The adversary sends some test commands to make sure the connection is working.

Techniques used

  • Connect a device such as a BusPirate or UM232H to the JTAG interface and connect using pin layout found from the JTAGulator
3

Exploit

Move along debug chain

Once the adversary has connected to the main TAP, or JTAG interface, they will move along the TAP chain to see what debug interfaces might be available on that chain.

Techniques used

  • Run a command such as “scan_chain” to see what TAPs are available in the chain.

Requirements

What does the attack require?

Prerequisites

  • Hardware device has an exposed debug interface

Skills required

  • Medium: Ability to identify physical debug interfaces on a device
  • Medium: Ability to operate devices to scan and connect to an exposed debug interface

Resources required

  • A device to scan a TAP or JTAG interface, such as a JTAGulator
  • A device to communicate on a TAP or JTAG interface, such as a BusPirate

Impact

What does a successful attack lead to?

Read Data

Affected scopes: Confidentiality

Modify Data

Affected scopes: Integrity

Gain Privileges

Affected scopes: Access Control, Authorization

Defence

How is it prevented and mitigated?

1
Implement: Ensure that debug components are properly chained, and their granularity is maintained at different authorization levels
2
Perform Post-silicon validation tests at various authorization levels to ensure that debug components are only accessible to authorized users

Real world

MITRE example instances

Example instance 1Detail
A System-on-Chip (SoC) might give regular users access to the SoC-level TAP, but does not want to give access to all of the internal TAPs (e.g., Core). If any of the internal TAPs were incorrectly chained to the SoC-level TAP, this would grant regular users access to the internal TAPs and allow them to execute commands there.
Example instance 2Detail
Suppose there is a hierarchy of TAPs (TAP_A is connected to TAP_B and TAP_C, then TAP_B is connected to TAP_D and TAP_E, then TAP_C is connected to TAP_F and TAP_G, etc.). Architecture mandates that the user have one set of credentials for just accessing TAP_A, another set of credentials for accessing TAP_B and TAP_C, etc. However, if, during implementation, the designer mistakenly implements a daisy-chained TAP where all the TAPs are connected in a single TAP chain without the hierarchical structure, the correct granularity of debug components is not implemented, and the attacker can gain unauthorized access.